A polishing technique is often used to planarize surfaces of an integrated circuit device during the various stages of the device's fabrication. Chemical Mechanical Polishing (CMP) is a typical procedure that involves combinations of chemical and mechanical process steps to effect planarization.
The degree of planarization achieved by CMP can be affected by the density and uniformity of metallic components in a surface to be polished. A more uniform metal density assists in achieving a good polishing. Thus, various design and manufacturing processes have developed density parameters for metal. In order to improve metallic density on a surface or layer of a chip, it is known to insert dummy tiles. A dummy tile is essentially a metallic tile or piece which is placed on a surface or layer of an integrated circuit. Dummy tiles can be strategically placed on a surface to improve density, and thereby improve polishing.
The performance of certain device components can be adversely affected if, for example, metal is placed non-symmetrically around them. The potential for an adverse affect from metallic tiles is particularly present when matched devices are utilized. In particular, the performance of those components that have critically matched structures may be degraded by poor metal tile placement. If not positioned symmetrically with respect to each component piece in a critically matched device, a metal tile may induce a mismatch and/or a parasitic capacitance. Thus, for example, previous designs have opted not to place dummy tiles above certain components such as resistors and capacitors. Nevertheless, certain resistor and capacitor devices are so large that if the area around them is not tiled, it will lead to insufficient metal density in the area of the device.
In complex devices having small gate dimensions, an integrated circuit may contain numerous devices in a variety of locations, and the metallic density around each device may be different. Thus, the tiling design may involve numerous and tedious calculations. As the design of integrated circuits becomes increasingly complex, it is desired to provide for a tiling design in an automated procedure.
Accordingly, it is desirable to develop a new method of tiling analog circuits that yields improved results and is relatively inexpensive to use. It would be desirable to develop a system and method for improving the metallic density in spaces and areas around matched circuit components such as resistors and capacitors. It would also be desirable that any process that attempts to provide metallic tiling around such a device be an automated process that takes into account the volume of calculations to be done. By virtue of the foregoing, it would further be desirable to develop a new tiling method that allows for improved CMP planarization around resistor and capacitor devices. Still further it would be advantageous if the new tiling method were compatible with existing processing equipment and materials that is used in semiconductor manufacturing processes. Other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.